Engineering Seminar Topics, Seminar Topics

Download Full Article VoIP

The telephone network is the most common of today’s voice communication facilities. However a silent revolution that is taking place on telephone networks; that revolution a voice over IP. That enable us to voice communication over the internet protocol, which is cheaper than voice communication through telephone network. In general VOIP refers to transport of new time media such as voice and video over the Internet to provide interactive communication among the Internet. Basic differences in technology used in VOIP and conventional telephone network is that, in VOIP packet switching is used but in telephone network, circuit switching is used. But quality of voice over IP is poor. Voice traveling over congested data network is a good as no voice at W1. The quality can be improved by having more bandwidth and providing primary voice in the various results on the net.

INTRODUCTION

The public telephone network and the equipment that makes it possible are taken for granted in most parts of the world. Availability of a telephone and access to a low cost ,high quality worldwide network is considered to be essential in modern society .Anything that would jeopardize this is usually since more and more communication is in digital format and transported via packet networks such as IP,ATM cells etc. Since data traffic is growing much faster than telephone traffic, there has been considerable interest in transporting voice over data networks.

Support for voice communication using the Internet Protocol (IP), which is usually just called “voice over IP” or VoIP, has been become especially attractive given the cost, flat rate pricing of the public internet. In fact, toll quality telephone over IP has now become one of the key steps leading to the convergence of the voice, video, and data communication industries. The feasibility carrying voice and call signaling messages over the Internet has already been demonstrated but delivering high quality commercial products, establishing public services, and convincing users to buy in to the vision are just beginning.

VoIP can be defined as the ability make telephone calls and to send facsimiles or IP based data networks with suitable quality of service (QoS) and much superior cost / benefit. Equipments producers   see VoIP   as a new opportunity to innovate compete. The challenge for them is turning this vision in to reality by quickly developing new VoIP enabled equipments. For Internet service providers the possibility of introducing usage based pricing and increasing their traffic volumes is very attractive. Users are seeking new types of integrated voice / data application as well as cost benefits.

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Download Full Article  Electrophysiological Interactive Computer Systems

New interactive computing applications are continually being developed in a bid to support people’s changing work and recreational activities.  As research focuses on one particular class interactive systems, high level models of interaction are formulated and requirements emerge that reflect shared features or common functionality among those systems.  The existence of models of interaction and shared functional requirements mean that support tools can be created which ease the subsequent development of these systems.  The type of tool that interactive systems developers are most familiar with is a library of reusable code that can be used for prototyping and building interactive applications and their interfaces.

A new class of interactive system  is identified, based on shared requirements for detection, processing and presentation of human physiological information.  This is electro physiological interactive computers systems.  It is envisaged that the work will serve as a jumping of point for others interested in exploring the potential of incorporating physiological information into the human machine relationship.  A method of hands free of human computer interaction currently under investigation is based on the detection of consciously controllable human physiological information.  This physiological information can be processed electrically and thereafter transformed into computer control signals and commands. 

INTRODUCTION

EPICS is a new class of interactive system based on detection, processing and presentation of human physiological information .A user physically manipulates an electromechanical device to initiate a computer operation requires the periodic dedication one or both hands. Unfortunately many people work in environments where their hands are fully occupied with other physical tasks. Examples include surgeons, fitters, maintenance engineers, aircraft flight crew and drivers of heavy goods, passenger and private vehicles. In all of these situations, access to information would be better served by alternative, hands-free access control. A further limitation of existing mechanical models of interaction is that they exclude access to those individuals for whom normal physical control is either difficult or impossible. It is clear that supplemental methods of human-machine interaction to those currently available are needed.

EPICS are interactive systems in which the physiological information can be processed electrically and thereafter transformed into computer control signals and commands. Using specialised electronic sensing equipment it is possible to both detect and make available in digital format information pertaining to a wide range of human physiology. Physiological sensing equipment can be used in order to train individuals to gain conscious control over a range of physiological parameters including heart rate, muscle tension and brain activity. The process of making physiological information available to a subject who is being trained to control some aspect of his or her own physiology is known as bio feed back. After training, physiological signals can be applied to hands free human machine control. It can utilize electrical brain activity to directly control a cursor on a computer screen and to input alphanumeric character using a soft keyboard….

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Download Full Article Smart Memories

                Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and low costs of widely applicable general-purpose designs. To address these conflicting requirements, here propose a modular reconfigurable architecture called Smart Memories, targeted at computing needs in the 0.1mm technology generation. A Smart Memories chip is made up of many processing tiles, each containing local memory, local interconnect, and a processor core. For efficient computation under a wide class of possible applications, the memories, the wires, and the computational model can all be altered to match the applications. To show the applicability of this design, two very different machines at opposite ends of the architectural spectrum, the Imagine stream processor and the Hydra speculative multiprocessor, are mapped onto the Smart Memories computing substrate. Simulations of the mappings show that the Smart Memories architecture can successfully map these architectures with only modest performance degradation.

INTRODUCTION

            The continued scaling of integrated circuit fabrication technology will dramatically affect the architecture of future computing systems. Scaling will make computation cheaper, smaller, and lower power, thus enabling more sophisticated computation in a growing number of embedded applications. This spread of low-cost, low power computing can easily be seen in today’s wired (e.g. gigabit Ethernet or DSL) and wireless communication devices, gaming consoles, and handheld PDAs. These new applications have different characteristics from today’s standard workloads, often containing highly data-parallel streaming behavior. While the applications will demand ever-growing compute performance, power (ops/W) and computational efficiency (ops/$) are also paramount; therefore, designers have created narrowly focused custom silicon solutions to meet these needs.

                 However, the scaling of process technologies makes the construction of custom solutions increasingly difficult due to the increasing complexity of the desired devices. While designer productivity has improved over time, and technologies like system-on-a-chip help to manage complexity, each generation of complex machines is more expensive to design than the previous one. High non-recurring fabrication costs (e.g. mask generation) and long chip manufacturing delays mean that designs must be all the more carefully validated, further increasing the design costs. Thus, these large complex chips are only cost-effective if they can be sold in large volumes. This need for a large market runs counter to the drive for efficient, narrowly- focused, custom hardware solutions.

                 To fill the need for widely applicable computing designs, a number of more general-purpose processors are targeted at a class of problems, rather than at specific applications. Tri-media, Equator, Mpact, IRAM, and many other projects are all attempts to create general purpose computing engine for multi-media applications. However, these attempts to create more universal computing elements have some limitations. First, these machines have been optimized for applications where the parallelism can be expressed at the instruction level using either VLIW or vector engines. However, they would not be very efficient for applications that lacked parallelism at this level, but had, for example, thread level parallelism. Second, their globally shared resource models (shared multi-ported registers and memory) will be increasingly difficult to implement in future technologies in which on-chip communication costs are appreciable. Finally, since these machines are generally compromise solutions between true signal processing engines and general-purpose processors, their efficiency at doing either task suffers.

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Download Full Article Neural Networks and Their Applications

1.1 What is a Neural Network?

An Artificial Neural Network (ANN) is an information-processing paradigm that is inspired by the way biological nervous systems, such as the brain, process information. The key element of this paradigm is the novel structure of the information processing system. It is composed of a large number of highly interconnected processing elements (neurons) working in unison to solve specific problems. ANNs, like people, learn by example. An ANN is configured for a specific application, such as pattern recognition or data classification, through a learning process. Learning in biological systems involves adjustments to the synaptic connections that exist between the neurons. This is true of ANNs as well. 

1.2 Historical background

Neural network simulations appear to be a recent development. However, this field was established before the advent of computers, and has survived several eras. Many important advances have been boosted by the use of inexpensive computer emulations. The first artificial neuron was produced in 1943 by the neurophysiologist Warren McCulloch and the logician Walter Pitts.

1. First Attempts: There were some initial simulations using formal logic. McCulloch and Pitts (1943) developed models of neural networks based on their understanding of neurology. These models made several assumptions about how neurons worked. Their networks were based on simple neurons, which were considered to be binary devices with fixed threshold.

2. Promising & Emerging Technology: Not only was neuroscience, but psychologists and engineers also contributed to the progress of neural network simulations. Rosenblatt (1958) stirred considerable interest and activity in the field when he designed and developed the Perceptron. The Perceptron had three layers with the middle layer known as the association layer. This system could learn to connect or associate a given input to a random output unit.

Another system was the ADALINE (Adaptive Linear Element) which was developed in 1960 by Widrow and Hoff (of Stanford University). The ADALINE was an analogue electronic device made from simple components. The method used for learning was different to that of the Perceptron, it employed the Least-Mean-Squares (LMS) learning rule.

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Download Full Article PARALLEL COMPUTING IN INDIA

            Although the performance of single processors has been steadily increasing over the years, the only way to build the next generation teraflop architecture supercomputers seems to be through parallel processing technology. Even with today’s workstation-class high performance processors exceeding 100 megaflops, thousands of processors are required to build a teraflop architecture machine. Further, the fastest special purpose vector processors have a few Gigaflop peak performance, and thus they too need to be utilized in parallel to achieve Teraflop levels of performance.

            In 1987, India decided to launch a national initiative in supercomputing in the form of a time-bound mission to design, develop and deliver a supercomputer in the gigaflops range. The major motivation came from delays (political) in getting a CRAY XMP for weather forecasting. A decision was made to support the development of indigenous parallel processing technology. The Center for Development of Advanced Computing (C-DAC) was set up in August 1988 with 3-year budget of Rs. 375 million (approximately US$ 12 million).

         C-DAC’s First Mission was directed to deliver 1000 MFlops parallel supercomputer (1GF) by 1991. Simultaneously, several other complementary projects were initiated to develop high-performance parallel computers at the National Aerospace Laboratory of the Council of Scientific and Industrial Research (CSIR), the Center for Development of Telematics (C-DOT), Advanced Numerical Research & Analysis Group (ANURAG) of Defense Research and Development Organization (DRDO) and Bhabha Atomic Research Center (BARC). India’s first generation parallel computers were delivered starting from 1991.

PARALLEL PROCESSING

              We all know that the silicon based chips are reaching a physical limit in processing speed, as they are constrained by the speed of electricity, light and certain thermodynamic laws. A viable solution to overcome this limitation is to connect multiple processors working in coordination with each other to solve grand challenge problems. Hence, high performance computing requires the use of Massively Parallel Processing (MPP) systems containing thousands of power full CPUs.

        Processing of multiple tasks simultaneously on multiple processors is called Parallel Processing. The parallel program consists of multiple active processes simultaneously solving a given problem. A given task is divided into multiple sub tasks using divide-and-conquer technique and each one of them are processed on different CPUs. Programming on multiprocessor system using divide-and-conquer technique is called Parallel Processing.

The development of parallel processing is being influenced by many factors. The prominent among them include the following:

Ø  Computational requirements are ever increasing, both in the area of scientific and business computing. The technical computing problems, which require high-speed computational power, are related to life sciences, aerospace, geographical information systems, mechanical design and analysis, etc.

Ø  Sequential architectures reaching physical limitation, as they are constrained by the speed of light and thermodynamics laws. Speed with which sequential CPUs can operate is reaching saturation point ( no more vertical growth ), and hence an alternative way to get high computational speed is to connect multiple CPUs ( opportunity for horizontal growth ).

Ø  Hardware improvements in pipelining, super scalar, etc, are non scalable and requires sophisticated compiler technology. Developing such compiler technology is difficult task.

Ø  Vector processing works well for certain kind of problems. It is suitable for only scientific problems ( involving lots of matrix operations). It is not useful to other areas such as database.

Ø  The technology of parallel processing is mature and can be exploited commercially, there is already significant research and development work on development tools and environment is achieved.

Ø  Significant development in networking technology is paving a way for heterogeneous computing.

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