Download Full Article
In the past three years several multiple data path and pipelined digital signal processors have been introduced into the marketplace. This new generation of DSP’s takes advantage of higher levels of integrations than were available for their predecessors. The Tiger SHARC processor is the newest and most power member of this family which incorporates many mechanisms like SIMD, VLIW and short vector memory access in a single processor. This is the first time that all these techniques have been combined in a real time processor.
The TigerSHARC DSP is an ultra high-performance static superscalar architecture that is optimized for tele-communications infrastructure and other computationally demanding applications. This unique architecture combines elements of RISC, VLIW, and standard DSP processors to provide native support for 8, 16, and 32-bit fixed, as well as floating-point data types on a single chip.
Large on-chip memory, extremely high internal and external bandwidths and dual compute blocks provide the necessary capabilities to handle a vast array of computationally demanding, large signal processing tasks.
2. DIGITAL SIGNAL PROCESSOR
Strictly speaking, the term “DSP” applies to any microprocessor that operates on digitally represented signals. In practice, however, the term refers to microprocessors specifically designed to perform digital signal processing tasks. Because most signal processing systems perform complicated mathematical operations on real-time signals, DSPs use special architectures to accelerate repetitive, numerically intensive calculations. For example, DSP architectures commonly include circuitry to rapidly perform multiply accumulate operations, which are useful in many signal-processing algorithms. Also, DSPs often contain multiple-access memory architectures that allow the processor to simultaneously load multiple operands. In addition, DSPs often include a variety of special memory addressing modes and program-flow control features designed to accelerate the execution of repetitive operations. Lastly, most DSP processors include specialized on-chip peripherals or I/O interfaces that allow the processor to efficiently interface with other system components, such as analog-to-digital converters and host processors.
Before going into the details of the Tiger SHARC architecture let us familiarize with a few architectural techniques which are the key elements of this new DSP.
1. VLIW- Very Long Instruction Word
VLIW points to the instructions that specify more than one concurrent operation in a single instruction. The following features characterize it: -
Ø Instruction width is quite large taking many bits to encode multiple operations.
ØRely on software to pack the collection of operation (compaction).
ØIn code with limited instruction parallelism, most of the instruction is wasted with no operation.
2. SIMD: - Single Instruction Multiple Data
A very important class of architectures in the history of computation, single-instruction/multiple-data machines is capable of applying the exact same instruction stream to multiple streams of data simultaneously. For certain classes of problems, e.g., those known as data-parallel problems, this type of architecture is perfectly suited to achieving very high processing rates, as the data can be split into many different independent pieces, and the multiple instruction units can all operate on them at the same time.
SIMD (Single-Instruction Stream Multiple-Data Stream) architectures are essential in the parallel world of computers. Their ability to manipulate large vectors and matrices in minimal time has created a phenomenal demand in such areas as weather data and cancer radiation research. The power behind this type of architecture can be seen when the number of processor elements is equivalent to the size of your vector. In this situation, component wise addition and multiplication of vector elements can be done simultaneously. Even when the size of the vector is larger than the number of processors elements available, the speedup, compared to a sequential algorithm, is immense. There are two types of SIMD architectures. The first is the True SIMD followed by the Pipelined SIMD. Each has its own advantages and disadvantages but their common attribute is superior ability to manipulate vectors.
The CPU can perform high-speed arithmetic operations within one instruction cycle because of its parallel and combinational architectural design. There are two execution units in the processor in order to facilitate the SIMD mode of operation of the processor. Only one execution unit is used in case of SISD operation. The SIMD mode is characterized by multiple instances of the same operation on different data.